Regviz

NXP Semiconductors /LPC18xx /CGU /BASE_PHY_RX_CLK

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as BASE_PHY_RX_CLK

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC18xx/CGU/BASE_PHY_RX_CLK#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OUTPUT_STAGE_ENABLED)PD 0RESERVED0 (DISABLED)AUTOBLOCK 0RESERVED0 (32_KHZ_OSCILLATOR)CLK_SEL0RESERVED

AUTOBLOCK=DISABLED, CLK_SEL=32_KHZ_OSCILLATOR, PD=OUTPUT_STAGE_ENABLED

Description

Output stage BASE_PHY_RX_CLK control register

Fields

PD

Output stage power down

0 (OUTPUT_STAGE_ENABLED): Output stage enabled (default)

1 (POWER_DOWN): power-down
RESERVED

Reserved
AUTOBLOCK

Block clock automatically during frequency change

0 (DISABLED): Disabled. Autoblocking disabled

1 (ENABLED): Enabled. Autoblocking enabled
RESERVED

Reserved
CLK_SEL

Clock source selection. All other values are reserved.

0 (32_KHZ_OSCILLATOR): 32 kHz oscillator

1 (IRC_DEFAULT): IRC (default)

2 (ENET_RX_CLK): ENET_RX_CLK

3 (ENET_TX_CLK): ENET_TX_CLK

4 (GP_CLKIN): GP_CLKIN

6 (CRYSTAL_OSCILLATOR): Crystal oscillator

8 (PLL0_FOR_AUDIO): PLL0 (for audio)

9 (PLL1): PLL1

12 (IDIVA): IDIVA

13 (IDIVB): IDIVB

14 (IDIVC): IDIVC

15 (IDIVD): IDIVD

16 (IDIVE): IDIVE
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data